1. Field of the Invention
The present invention relates to an electrically erasable and programmable semiconductor memory device, more particularly, to a semiconductor memory device which implements a variable capacity by enabling the writing of binary or multivalued information.
2. Description of the Related Art
In general, electronic equipment is provided with memories for storing a program for controlling its operation, various data such as audio data and image data, or the like. Generally, a flash memory capable of high-speed random access is used to store the control program, and a flash memory with large capacity is used to store the data.
The electronic equipment must have therefore two types of flash memories, i.e., a low-speed but large-capacity memory and a high-speed but small-capacity random access memory, as shown in FIG. 7A. Moreover, in a designing stage, most of the flash memories for storing the control program must be designed so that capacity of the memory is enough large to store any potential program, since there exists possibility to change a size of the program to be stored. Consequently, the flash memory of large size is often designed. Thus, when the control program actually developed is small in size as shown in FIG. 7B, a problem of a useless area exists because the memory size cannot be changed later. This problem can be solved by using the flash memory for high-speed random access for both of the control program and the data, as shown in FIG. 7C. However, such a solution has a problem of an increase in manufacturing costs because the flash memory for high-speed random access is expensive.
The invention is directed to solve the foregoing problems, that is, to provide a semiconductor memory device capable of realizing an efficient use of a memory area and reducing the manufacturing costs.
In a first aspect of the invention, a nonvolatile semiconductor memory device capable of electrical data writing and data reading, comprises a memory cell array, a word line driver, a voltage controller and a binary/multivalued controller.
The memory cell array comprises a plurality of memory cells and has a data storing area or a memory space divided into a plurality of areas. Each of the areas selectively is set to a binary area for storing binary data or a multivalued area for storing multivalued data. The word line driver supplies a driving voltage to a word line of the memory cell array. The voltage controller controls an output voltage of the word line driver. The binary/multivalued controller controls the voltage controller so as to switch the output voltage of the word line driver in accordance with whether the data is to be recorded to the cell in the form of the binary data or the multivalued data.
The memory device may further comprise a unit for storing information which indicates whether the divided area of the memory cell array is the binary area or the multivalued area. Each divided area of the memory cell array can be set arbitrarily to either of the binary area or the multivalued area in a memory address space.
The memory device may further comprise a switching unit for switching a method of outputting data to an external device in accordance with whether the data is recorded in the form of binary data or multivalued data.
The memory device may further comprise a switching unit for switching a method of writing data in accordance with the data is to be recorded in the form of binary data or multivalued data.
The memory device may further comprise an output unit for outputting latency information corresponding to the address of the data to be read.
The memory device may further comprise a unit for changing a predetermined parameter related to synchronous burst reading in accordance with the address at a synchronous burst reading operation.
The memory device may further comprise a bit line selecting unit for selecting a plural predetermined number of bit lines on data reading. One data value may be read out from a predetermined number of memory cells connected to one word line and the predetermined number of bit lines selected by the bit line selecting unit.
In the memory device, the multivalued sense amplifier may read the multivalued data by using a delay during the reading operation of the data from the memory cell.
In a second aspect of the invention, a nonvolatile semiconductor memory device capable of electrically writing and reading data, comprises a memory cell array, a binary sense amplifier, a multivalued sense amplifier and a binary/multivalued controller.
The memory cell array comprises a plurality of memory cells and has a data storing area or a memory space divided into a plurality of areas. Each of the divided areas is set selectively to a binary area for storing binary data or a multivalued area for storing multivalued data. The binary sense amplifier is used when the binary data is read out from the memory cell. The multivalued sense amplifier is used when the multivalued data is read out from the memory cell. The binary/multivalued controller selects, as a sense amplifier to be used in data reading, the binary sense amplifier when the data is read from the binary area, or the multivalued sense amplifier when the data is read from the multivalued area.
According to the invention, one semiconductor memory can record the data as both of the binary data and the multivalued data (for example, four valued data), and the capacity can be freely changed. It is therefore possible to realize the semiconductor memory capable of improving the efficiency of the use of the memory area and reducing manufacturing costs.
It should be noted that this application is based on application No. 2000-10442 filed in Japan, the contents of which is incorporated herein by reference.